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INTEGRATED CIRCUITS
DATA SHEET
SAA7191B Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
Product specification File under Integrated Circuits, IC22 August 1996
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION LIMITING VALUES CHARACTERISTICS I2C-BUS FORMAT PROGRAMMING EXAMPLE PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
SAA7191B
August 1996
2
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
1 FEATURES 2 GENERAL DESCRIPTION
SAA7191B
* Separate 8-bit luminance (Y or CVBS) and 8-bit chrominance inputs (CVBS or C) from CVBS, Y/C, S-Video (S-VHS or Hi8) sources * Luminance and chrominance signal processing for standards PAL-B/G, NTSC-M, SECAM * Horizontal and vertical sync detection for all standards * Real-time control output RTCO to be used for frequency-locked digital video encoder (SAA7199B). RTCO contains serialized information about actual clock frequency, subcarrier frequency and PAL/SECAM sequence. * Controls via the I2C-bus * User programmable aperture correction (horizontal peaking) * Compatible with memory-based features (line-locked clock) * Cross-colour reduction by chrominance comb-filtering (NTSC) or by special cross colour cancellation (SECAM) * 8-bit quantization of input signals * 768/640 active samples per line equals 50/60 Hz (SQP) * The YUV bus supports data rates of 780 x fH equal to 12.2727 MHz for 60 Hz (NTSC-M) and 944 x fH equal to 14.75 MHz for 50 Hz (PAL-B/G, SECAM) in 4 : 1 : 1 or 4 : 2 : 2 formats (via the I2C-bus) * One crystal oscillator of 26.8 MHz 3 QUICK REFERENCE DATA SYMBOL VDD IDD VIL VOL Tamb 4 PARAMETER
The SAA7191B is a digital multistandard colour decoder suitable for 8-bit CVBS input signals or for 8-bit luminance and 8-bit chrominance input signals (Y/C). The SAA7191B is down-compatible with SAA7191. The SAA7191B has additional outputs RTCO, GPSW0 and ODD. These new outputs are in high-impedance state when NFEN-bit = 0.
MIN. 4.5
TYP. 5 100
MAX. 5.5 250
UNIT V mA
positive supply voltage (pins 5, 18, 28, 37 and 52) total supply current (pins 5, 18, 28, 37 and 52) input levels output levels operating ambient temperature
TTL-compatible TTL-compatible 0 70 C
ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS 68 PIN POSITION PLCC MATERIAL plastic CODE SOT188-2
SAA7191B
August 1996
3
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+5 V PLIN VDD1 to VDD4 5, 18. 28, 52 VSS1 to VSS4 19, 38, 51, 67 66 68 44 1, 2 CVBS7 to CVBS0 14 to 17 20 to 23 CHROMINANCE PROCESSOR 55 to 62 INPUT INTERFACE CHR7 to CHR0 6 to 13 LUMINANCE PROCESSOR OUTPUT INTERFACE 42 63
5
Philips Semiconductors
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
BLOCK DIAGRAM
RTCO
handbook, full pagewidth
internally connected
test pins
SAA7191B
45 to 50, 53, 54
Y output (Y7 to Y0) UV output (UV7 to UV0) HREF FEON
4
GPSW0 GPSW1 GPSW2 65 24 25 SDA 40 41 IICSA RESN
64 PORT AND STATUS REGISTER clock status 35 I 2 C-BUS CONTROL CLOCK 33 37 +5 V
FEIN VDDA
VSSA XTAL XTALI
SYNCHRONIZATION
34 43 3 26 HCL 29 HSY 30 VS 31 HS 32 HL 36 LFCO 39 ODD 4 CREF 27
Product specification
SAA7191B
LLC
MEH435
Fig.1 Block diagram. Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
6 PINNING SYMBOL SP AP RESN CREF VDD1 CHR0 CHR1 CHR2 CHR3 CHR4 CHR5 CHR6 CHR7 CVBS0 CVBS1 CVBS2 CVBS3 VDD2 VSS1 CVBS4 CVBS5 CVBS6 CVBS7 GPSW1 GPSW2 HCL LLC VDD3 HSY VS HS HL XTAL XTALI VSSA LFCO VDDA VSS2 ODD SDA August 1996 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Port 1 output for general purpose (programmable) Port 2 output for general purpose (programmable) black level clamp pulse (programmable), e.g. for TDA8708 (ADC) +5 V supply input 2 ground 1 (0 V) chrominance input data bits CHR7 to CHR0 from a Y/C (VHS, Hi8) source in two's complement format DESCRIPTION connected to ground (shift pin for testing) connected to ground (action pin for testing) reset, active LOW
SAA7191B
clock reference, sync from external to ensure in-phase signals on the YUV-bus +5 V supply input 1
luminance respectively CVBS lower input data bits CVBS3 to CVBS0 (CVBS with luminance, chrominance and all sync information in two's complement format)
luminance respectively CVBS upper input data bits CVBS7 to CVBS4 (CVBS with luminance, chrominance and all sync information in two's complement format)
line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system) +5 V supply input 3 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC) vertical sync output signal horizontal sync output signal (programmable) horizontal lock flag, HIGH = PLL locked 26.8 MHz clock output 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave) analog ground line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz) +5 V supply input for analog part ground 2 (0 V) odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1 I2C-bus data line 5
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SYMBOL SCL HREF IICSA i.c. Y7 Y6 Y5 Y4 Y3 Y2 VSS3 VDD4 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 FEON FEIN GPSW0 PLIN VSS4 RTCO PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 output active flag (active LOW when Y and UV data in high-impedance state) fast enable input (active LOW to control fast switching due to YUV data) Port 0 output for general purpose (programmable); active only at NFEN-bit = 1 ground 3 (0 V) +5 V supply input 4 Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus I2C-bus clock line DESCRIPTION
SAA7191B
horizontal reference output for valid YUV data (for active line 768Y or 640Y samples long) set module address input (LOW = 1000 101X; HIGH = 1000 111X) internally connected
UV signal output bits UV7 to UV0 (colour-difference), part of the digital YUV-bus
PAL flag (active LOW at inverted line); SECAM flag (LOW equals DR, HIGH equals DB line) ground 4 (0 V) real-time control output active at NFEN-bit = 1; Fig.8
August 1996
6
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
6.1 Pin configuration
SAA7191B
V DD4
UV2
UV3
UV4
UV5
UV6
UV7
V SS3
handbook, full pagewidth
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
UV1 UV0 FEON FEIN GPSW0 PLIN
i.c. 44
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
61 62 63 64 65 66
43 IICSA 42 HREF 41 SCL 40 SDA 39 ODD 38 V SS2 37 V DDA 36 LFCO
V SS4 67 RTCO 68 SP AP RESN CREF V DD1 CHR0 CHR1 CHR2 CHR3 1 2 3 4 5 6 7 8 9
SAA7191B
35 V SSA 34 XTALI 33 XTAL 32 HL 31 HS 30 VS 29 HSY 28 V DD3 27 LLC
10 CHR4
11 CHR5
12 CHR6
13 CHR7
14 CVBS0
15 CVBS1
16 CVBS2
17 CVBS3
18 V DD2
19 V SS1
20 CVBS4
21 CVBS5
22 CVBS6
23 CVBS7
24 GPSW1
25 GPSW2
26 HCL
MEH436
Fig.2 Pin configuration.
August 1996
7
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
7 7.1 FUNCTIONAL DESCRIPTION Chrominance processor
SAA7191B
The 8-bit chrominance input signal (CVBS or chrominance format) passes a bandpass filter to eliminate DC components and to decimate the sample rate before it is fed to the two multipliers (quadrature demodulator), Fig.3. Two subcarrier signals from a local oscillator (0 to 90 degree) are fed to the multiplicator inputs of the multipliers. The multipliers operate as a quadrature demodulator for all PAL and NTSC signals; it operates as a frequency down-mixer for SECAM signals. The two multiplier output signals are converted to a serial data stream and applied to three low-pass filter stages, then to a gain controlled amplifier. A final multiplexed low-pass filter achieves, together with the preceding stages, the required bandwidth performance. The signals, originated from PAL and NTSC, are applied to a comb-filter. The signals, originated from SECAM, are fed through a Cloche filter (0 Hz centre frequency), a phase demodulator and a differentiator to obtain frequency-demodulated colour-difference signals.The SECAM signals are fed after de-emphasis to a cross-over switch, to provide the both serial-transmitted colour-difference signals. These signals are fed finally to the output formatter stages and to the output interface.
August 1996
8
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CVBS (7-0) INPUT INTERFACE CHR (7-0) CHROMINANCE BANDPASS QUADRATURE DEMODULATOR LOWPASS FILTER BYPS CHRS HUEC FISE SECS NFEN DISCRETE TIME OSCILLATOR (DTO1) AND DIVIDER FISE RTCO 68 LOOP FILTER PI1 CKTS (4-0) CHCV (7-0) CKTO (4-0) LFIS (1-0) SECS
Philips Semiconductors
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
GAIN CONTROLLED AMPLIFIER
LOOP FILTER PI2
BURST GATE ACCUMULATOR
handbook, full pagewidth
UV (7-0) 42 LOWPASS FILTER QUAM COMB FILTERS AND SECAM RECOMBINATION OUTPUT FORMATTER AND OUTPUT INTERFACE 63 64 HREF FEON FEIN Y (7-0) SECS HRMV CLOCHE FILTER OFTS COLO OEDY OEDC OEHS
CODE
PHASE DEMODULATOR AND AMPLITUDE DETECTOR
9
PLIN 66 SEQUENCE PROCESSOR
DIFFERENTIATOR PLSE(7-0) SESE(7-0) FISE SECS SEQA
SAA7191B
CHROMINANCE
SXCR
DE-EMPHASIS
Product specification
SAA7191B
to luminance
from luminance
MEH437
Fig.3(a) Detailed block diagram; continued in Fig.3(b).
Fig.3 Detailed block diagram; continued in Fig.4.
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HRMV SCEN OEVS OEHS FISE RESN SCL SDA IICSA 3 41 40 43 NFEN I2C-BUS CONTROL COUNTER VERTICAL PROCESSOR
Philips Semiconductors
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
from input interface
handbook, full pagewidth
to output interface
SAMPLE RATE CONVERTER
PREFILTER
CHROMINANCE TRAP
VARIABLE BANDPASS FILTER
CORING
WEIGHTING AND ADDING STAGE
VARIABLE DELAY COMPENSATION
PREF
BYPS FISE
BPSS (1-0)
PREF BYPS
CORI (1-0)
APER (0-1)
YDEL (2-0)
LUMINANCE
MATCHING AMPLIFIER
FISE internal clocks
4 PREFILTER SYNC SYNC SLICER PHASE DETECTOR FINE PHASE DETECTOR COARSE LOOP FILTER PROGRAMMABLE DELAY LINE-LOCKED CLOCK GENERATOR 27
CREF LLC
SAA7191B
SYNC
HCLB (7-0) HCLS (7-0) HSYB (7-0) HSYS (7-0) HPHI (7-0) IDEL (7-0)
VTRC FISE HLCK STTC HLCK VTRC HPLL FISE 33 DISCRETE TIME OSCILLATOR (DTO2) CRYSTAL CLOCK GENERATOR 34 XTAL XTAL I
FISE FISE DAC FIDT
65,24,25
26
29
30
31
32
39
VNOI (1-0) HLCK VTRC FSEL AUFD NFEN
Product specification
36
SAA7191B
GPSW(2-0)
HCL HSY
VS
HS
HL
ODD
LFCO
MEH438-1
Fig.4 Detailed block diagram; continued from Fig.3. Fig.3(b) Detailed block diagram; continued from Fig.3(a).
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
7.2 Luminance processor Table 1
SAA7191B
Clock frequencies in MHz for 50/60 Hz systems 50 Hz 29.5 14.75 7.375 3.6875 Line locked clock frequency 60 Hz 24.545454 12.272727 6.136136 3.068181
The luminance input signal, a digital CVBS format or an 8-bit luminance format (S-VHS, Hi8), is fed through a sample rate converter to reduce the data rate to 14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC), Fig.4. Sample rate is converted by means of a switchable pre-filter. High frequency components are emphasized to compensate for loss in the following chrominance trap filter. This chrominance trap filter (fo = 4.43 MHz or fo = 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be by-passed for S-Video (S-VHS and Hi8) signals. The high frequency components of the luminance signal can be "peaked" (control for sharpness improvement via the I2C-bus) in two bandpass filters with selectable transfer characteristic. A coring circuit with selectable characteristic improves the signal once more, this signal is then added to the original ("unpeaked") signal. A switchable amplifier achieves a common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the variable delay compensation. 7.3 Processing delay
CLOCK LLC LLC2 LLC4 LLC8 7.5
LFCO is required in an external PLL (SAA7197) to generate the line locked clock frequency. 7.6 YUV-bus, digital outputs
The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or to the digital-to-analog converter (DAC). Outputs are controlled via the I2C-bus in normal selections, or they are controlled by output enable chain (FEIN on pin 64, Fig.5). The YUV-bus data rate equals LLC2 in Table 1. Timing is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference). YUV-bus formats 4:2:2 and 4:1:1 The output signals Y7 to Y0 are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits of the multiplexed colour-difference signals (B-Y) and (R-Y). The frame in the following tables is the time, required to transfer a full set of samples. In case of 4 : 2 : 2 format two luminance samples are transmitted in comparison to one U and one V sample within one frame.
The delay from input to output is 220 LLC cycles if YDEL is set to 0. The processing delay will be influenced in future enhancements. 7.4 Synchronization
The luminance output signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors to be compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Adjustable output signals (e. g. HCL and HSY) are generated according to peripheral requirements (TDA8708A, TDA8709A). The output signals HS, VS and PLIN are locked to the timing reference signal HREF (Figures 7 and 8). There is no absolute timing reference guaranteed between the input signal and the HREF signal as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications, which ask for absolute timing accuracy to the input signals. The loop filter signal drives an oscillator to generate the line frequency control output signal LFCO.
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
Table 2 4 : 2 : 2 format (768 pixels per line for 50 Hz system; 640 pixels per line for 60 Hz system) PIXEL BYTE SEQUENCE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 0 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 2 2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 4 4 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 5
SAA7191B
OUTPUT Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7(MSB) Y frame UV frame Notes 1. Data rate: LLC2 2. Sample frequency: Y LLC2 U LLC4 V LLC4
The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal.
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
Table 3
SAA7191B
4 : 1 : 1 format (768 pixels per line for 50 Hz system and 640 pixels per line for 60 Hz system) PIXEL BYTE SEQUENCE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V6 V7 U6 U7 0 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V4 V5 U4 U5 1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V2 V3 U2 U3 2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V0 V1 U0 U1 3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V6 V7 U6 U7 4 4 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V4 V5 U4 U5 5 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V2 V3 U2 U3 6 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V0 V1 U0 U1 7
OUTPUT Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7 (MSB) Y frame UV frame Notes 1. Data rate: sample frequency: Y U V LLC2 LLC2 LLC8 LLC8
Fast enable is achieved by setting input FEIN to LOW. This signal is used to control fast switching on the digital YUV-bus. HIGH on this pin forces the Y and U/V outputs to a high-impedance state. The signal FEON is LOW when the Y and U/V outputs are in this high-impedance state (Fig.5). The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal. Table 4 OEDY X 0 0 1 1 Digital output control OEDC X 0 1 0 1 FEIN 0 1 1 1 X Y(7:0) active Z Z active active UV(7:0) active Z active Z active FEON 1 0 1 1 1
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
LLC to 3-state CREF from 3-state
HREF tSU FEIN t OH YUV t OS tHD
FEON
MEH441-1
Fig.5 Timing example of fast enable input FEIN.
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full LLC pagewidth
CREF
internal bus clock
HREF
start of active line
Byte numbers for pixels: Y signal 50 Hz U and V signal U0 V0 U2 V2 U4 V4 U6 V6 0 1 2 3 4 5 6 7
Y signal 60 Hz U and V signal
0
1
2
3
4
5
6
7
U0
V0
U2
V2
U4
V4
U6
V6
MEH233-2
handbook, full pagewidth
LLC
CREF
HREF Byte number for pixels: Y signal 50 Hz U and V signal U762 V762 U764 V764 762 763 764 765
end of active line
766
767
U766
V766
Y signal 60 Hz U and V signal
634
635
636
637
638
639
U634
V634
U636
V636
U638
V638
MEH234-3
Fig.6 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
handbook, full pagewidth
SAA7191B
(a) 1st field input CVBS
625
1
2
3
4
5
6
7
8
9
HREF 541 x 2/LLC VS
ODD 2 x 2/LLC
(b) 2nd field input CVBS
313
314
315
316
317
318
319
320
321
HREF
VS
69 x 2/LLC
ODD
2 x 2/LLC
50 Hz
handbook, full pagewidth
MEH224-1
(a) 1st field input CVBS
525
1
2
3
4
5
6
7
8
9
HREF 449x 2/LLC VS
ODD
2 x 2/LLC
(b) 2nd field input CVBS
263
264
265
266
267
268
269
270
271
HREF 59 x 2/LLC VS 2 x 2/LLC ODD
60 Hz
Fig.7 Vertical timing diagram for 50 / 60 Hz.
MEH225-1
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
H/L transition (counter start) 128 clocks 13 HPLL increment bits 13 to 0 0
4 bits reserve FSCPLL increment bits 21 to 0 10
3 bits sequence bit (1) reserve reserved (2) 5 10
bit 22
20
15
RTCO 4 0 (1)Sequence bit: SECAM: 0 equals DB-line 1 equals DR-line PAL: 0 equals (R-Y) line normal 1 equals (R-Y) line inverted NTSC: 0 (no change) 8 14 19 time slot (LLC/4) valid not valid 63 67
MEH442
(2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems
Fig.8 RTCO timing.
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 19, 35, 38, 51 and 67 as well as supply pins 5, 18, 28, 37 and 52 connected together. SYMBOL VDD Vdiff GND VI VO Ptot Tstg Tamb VESD Note 1. Equivalent to discharging a 100 pF capacitor through an 1.5 k series resistor. PARAMETER supply voltage (pins 5, 18, 28, 37, 52) difference voltage VSS A - VSS (1 to 4) voltage on all inputs voltage on all outputs (IO max = 20 mA) total power dissipation storage temperature range operating ambient temperature range electrostatic handling(1) for all pins - -0.5 -0.5 - -65 0 - MIN. -0.5 MAX. 7.0 100 VDD+0.5 VDD+0.5 2.5 150 70 2000 V mV V V W C C V UNIT
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
9 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to 70 C unless otherwise specified. SYMBOL VDD IDD PARAMETER supply voltage range (pins 5, 18, 28, 37, 52) total supply current (pins 5, 18, 28, 37, 52) CONDITIONS MIN. 4.5 VDD = 5 V; inputs LOW; - outputs not connected -0.5 3 - acknowledge I40 = 3 mA 3 - -0.5 2.4 -0.5 2.0 - data inputs; note 1 I/O high-ohmic clock inputs Fig.9 - - - 11 3 5 100 TYP.
SAA7191B
MAX. 5.5 250
UNIT V mA
I2C-bus, SDA and SCL (pins 40 and 41) VIL VIH I40,41 IACK VOL VIL VIH VIL VIH ILI CI input voltage LOW input voltage HIGH input current output current on pin 40 output voltage at acknowledge - - - - - - - - - - - - - - - - - - - - - - - 1.5 10 0.4 V A mA V VDD+0.5 V
Data clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 43 and 64), Fig.11 LLC input voltage LOW (pin 27) LLC input voltage HIGH other input voltage LOW other input voltage HIGH input leakage current input capacitance 0.6 V VDD+0.5 V 0.8 V VDD+0.5 V 10 8 8 10 - - A pF pF pF ns ns
tSU.DAT tHD.DAT Vo V36 VOL VOH CL VOL VOH CL
input data set-up time input data hold time
LFCO output (pin 36) output signal (peak-to-peak value) output voltage range note 2 1.4 1 2.6 VDD 0.6 VDD 50 V V
YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62) output voltage LOW output voltage HIGH load capacitance notes 1 and 2
Figures 10 and 15 to 25 0 2.4 15 V V pF
Control outputs (pins 24 to 26, 29, 31, 32, 39, 63, 65, 66 and 68); Fig.12 output voltage LOW output voltage HIGH load capacitance notes 1 and 2 0 2.4 7.5 0.6 VDD 25 V V pF
August 1996
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Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SYMBOL PARAMETER CONDITIONS Fig.8 YUV, HREF, VS at CL = 15 pF controls at CL = 7.5 pF tOS output set-up time YUV, HREF, VS at CL = 50 pF; controls at CL = 25 pF tSZ tZS tRTCO fC fn f / fn X1 data output disable transition time data output enable transition time RTCO timing 400 Fig.10 3rd harmonic - - - 0 8 - - - Fig.9 note 3 tLLCH / tLLC 31 40 - - - - - - 26.8 - - - - 50 to 3-state condition from 3-state condition 13 13 14 14 16 14 - - - - - - Fig.8 - MIN. TYP.
SAA7191B
MAX. - - - - - -
UNIT
Timing of YUV-bus and control outputs tOH output signal hold time
ns ns ns ns ns ns
Chrominance PLL catching range - - 50 20 70 - 80 Hz
Crystal oscillator nominal frequency permissible deviation fn temperature deviation from fn crystal specification: temperature range Tamb load capacitance CL series resonance resistance RS motional capacitance C1 parallel capacitance C0 Philips catalogue number Line locked clock input LLC (pin 27) tLLC tp tr tf Notes cycle time duty factor rise time fall time
MHz 10-6 10-6 C pF fF pF
1.120% - 3.520% -
9922 520 30004
45 60 5 6
ns % ns ns
1. Data output signals are Y7 to Y0 and UV7 to UV0. All others are control output signals. 2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 k in parallel to 50 pF at 3 V (TTL load); LFCO output with 10 k in parallel to 15 pF and other outputs with 1.2 k in parallel to 25 pF at 3 V (TTL load). 3. tSU, tHD, tOH and tOD include tr and tf.
August 1996
19
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
t LLC t LLC H 2.4 V
clock input LLC
1.5 V 0.6 V t SU t HD not valid tf tr
input data
2.0 V 0.8 V
2.0 V input CREF 0.8 V t ZS t OS t OH not valid 2.4 V output data 0.6 V t SU t HD
t SZ
t SU
t HD 2.4 V
input FEIN 0.6 V
MEH231-1
Fig.9 Data input and output timing diagram.
handbook, full pagewidth
26.8 MHz (3rd harmonic) 10 pF X1
(1)
XTAL
33
XTAL
33
SAA7191B
XTALI 34 XTALI
(1)
SAA7191B
34
1 nF
10 H 20 %
10 pF
(1) value depends on crystal parameters
(a)
(b)
MEH439
Fig.10 Oscillator application (a) and optional clock from external source (b).
August 1996
20
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
+127 +106 +95 reserved
+127
+76
luminance NTSC luminance PAL, SECAM 0 chrominance PAL and SECAM
chrominance NTSC 0
chrominance input range (red, cyan 75 %)
-52 -64
blanking level -76
-91 -103 sync -128 -132 -128
(a) CVBS7 to CVBS0 input signal range.
(b) CHR7 to CHR0 input signal range.
+255 +235 white 100 %
+255
+255
+212
blue 75 %
+212
red 75 %
luminance output range +128 +128 U-component output range +128 V-component output range
+44 +16 0 black 0
yellow 75 %
+44
cyan 75 %
0
(c) Y output signal range.
(d) U output signal range (B-Y).
(e) V output signal range (R-Y).
MEH254-1
1. All levels are related to EBU colour bar. 2. Values in decimal at 100% luminance and 75% chrominance amplitude.
Fig.11 Input and output signal ranges.
August 1996
21
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
62 x 2/LLC burst
CVBS
HSY HSY programming + 191 range (step size: 2/LLC) HCL HCL programming + 127 range (step size: 2/LLC) 220 LLC
processing delay CVBS - YUV at YDEL = 000 b
0
- 64
0
- 128
10 x 2/LLC
Y-output
HREF (50 Hz) 768 x 2/LLC 176 x 2/LLC
PLIN (50 Hz ) 38 x 2/LLC HS (50 Hz) 64 x 2/LLC HS (50 Hz) programming range (step size: 8/LLC) + 117 0 38 x 2/LLC HREF (60 Hz) 640 x 2/LLC 140 x 2/LLC - 118 100 x 2/LLC
HS (60 Hz)
64 x 2/LLC HS (60 Hz) programming range (step size: 8/LLC) + 97 0 - 97
MEH226-2
Fig.12 Horizontal sync at HRMV = 0 and HRFS = 0 for 50/60 Hz (signals HSY, HCL, HREF and PLIN).
August 1996
22
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full pagewidth
Y or CVBS Vi , source 2 75
1 F 680
19 20
+
+
+
August 1996 23
Philips Semiconductors
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
digital 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
signal source selected by GPSW1-bit (LOW = source 1)
chrominance Vi , source 1 75 chrominance Vi , source 2 75
digital 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 F
+
16 17
CHR0 CHR1 CHR2 CHR3
CHR7 to CHR0
1 F 680
+
18 19 20
Y or CVBS Vi , source 1 75
1 F
16 17 18
CVBS0 CVBS1 2.2 k CVBS2 CVBS3
0.1 F
23
2.2 k
0.1 F
1 F
21
+
1 F
21
VDDA
TDA8709A
22
VDDO 0.1 F VDDD CLK CHR4 CHR5 CHR6 CHR7
0.1 F
0.1 F 0.1 F VDDO 0.1 F
24
0.1 F
25
68 pF
VDDA
TDA8708A
22 23
4.7 k
26
VDDD CLK CVBS4 CVBS3 CVBS2 CVBS7 120 68 pF
18
analog 27 28
5.6
0.22 F
24
2.7 k
10 F
+
25 26
5.6
5.6
1 k
HSY 10
analog
27 28
CVBS7 to CVBS0
HCL LLCA +5 V (analog supply)
5.6
120
18
Product specification
SAA7191B
+5 V (digital supply)
MEH443
Fig.13 Application circuit for analog-to-digital conversions.
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
VSS i.c. 0.1 F 5 0.1 F 18 0.1 F 0.1 F
digital
horizontal lock flag
HL UV7 to UV0
67 51 38 19
44
32
28 52
62 61 60 59 58 57 56 55 54 53 50 49 48 47 46 45 39 31 30 29 26
UV0 UV1 UV2 UV3 UV4 UV5 UV6 UV7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 ODD HS VS HSY HCL HREF SCL SDA RTCO GPSW0
YUV-bus
+5 V
chrominance CHR7 to CHR0
VDD
CHR0 CHR1 CHR2 CHR3 CHR4 CHR5 CHR6 CHR7
Y7 to Y0
luminance CVBS7 to CVBS0
6 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 33
SAA7191B
L0 L1 L2 L3 L4 L5 L6 L7
handbook, full pagewidth
XTAL: Philips 9922 520 30004 X1 26.8 MHz
42 41 40 68 65 63 FEON 64 IICSA 43 2 1 35 VDDA 37
VSSA FEIN
I 2 C-bus
34 reset 10 pF 10 H 1 nF 10 pF 3 27 4
digital
24 25
36
66
PLIN
digital
+5 V 0.1 F 2.2 H 0.1 F 0.1 F
analog
LFCO
VDD analog
+5 V
S1 S2 RESN LLCA CREF LLCB LLC2A LLC2B
19 16
SAA7197
+
11
12 7 15 10 14 20
5 2 3 4 8 17 1 6 9 13 18
10 F
VDD digital 0.1 F 0.1 F
+5 V
digital
MEH440-1
Fig.14 Application circuit for digital multistandard colour decoder.
August 1996
24
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
10 I2C-BUS FORMAT S SLAVE ADDRESS A SUBADDRESS A DATA0 A
SAA7191B
DATAn
A
P
S SLAVE ADDRESS A SUBADDRESS(1) DATA P X
= = = = = = =
start condition 1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH) acknowledge, generated by the slave subaddress byte (Table 5) data byte (Table 5) stop condition read/write control bit X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter)
Note 1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed. Table 5 I2C-bus; DATA for status byte (X = 1 in address byte; 8Bh at IICSA = LOW or 8Fh at IICSA = HIGH). DATA FUNCTION D7 status byte STTC D6 HLCK D5 FIDT X D4 X D3 X D2 X D1 D0 CODE
Function of the bits: STTC Horizontal time constant information for future application with logical combfilter only: 0 = TV time constant (slow); 1 = VCR time constant (fast) HLCK FIDT CODE Horizontal PLL information: Field information: Colour information: 0 = HPLL locked; 1 = HPLL unlocked 0 = 50 Hz system detected; 1 = 60 Hz system detected 0 = no colour detected; 1 = colour detected
August 1996
25
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
Table 6
SAA7191B
I2C-bus; subaddress and data bytes for writing (X = 0 in address byte; 8Ah at IICSA = LOW or 8Eh at IICSA = HIGH). DATA SUBADDRESS D7 D6 D5 D4 IDEL4 HSYB4 HSYS4 HCLB4 HCLS4 HPHI4 BPSS0 HUEC4 CKTQ1 CKTS1 PLSE4 SESE4 0 0 OEVS SCEN 0 CHCV4 0 0 HS6B4 HS6S4 HC6B4 HC6S4 HP6I4 D3 IDEL3 HSYB3 HSYS3 HCLB3 HCLS3 HPHI3 CORI1 HUEC3 CKTQ0 CKTS0 PLSE3 SESE3 0 NFEN OEDY OFTS 0 CHCV3 0 0 HS6B3 HS6S3 HC6B3 HC6S3 HP6I3 D2 IDEL2 HSYB2 HSYS2 HCLB2 HCLS2 HPHI2 D1 IDEL1 HSYB1 HSYS1 HCLB1 HCLS1 HPHI1 D0 IDEL0 HSYB0 HSYS0 HCLB0 HCLS0 HPHI0 APER0 HUEC0 0 0 PLSE0 SESE0 00 01 02 03 04 05 06 07 08 IDEL7 IDEL6 IDEL5 HSYB7 HSYB6 HSYB5 HSYS7 HSYS6 HSYS5 HCLB7 HCLB6 HCLB5 HCLS7 HCLS6 HCLS5 HPHI7 HPHI6 HPHI5 BYPS PREF BPSS1 HUEC7 HUEC6 HUEC5 CKTQ4 CKTQ3 CKTQ2 CKTS4 CKTS3 CKTS2 PLSE7 PLSE6 PLSE5 SESE7 SESE6 SESE5 COLO VTRC HPLL LFIS1 0 OEDC LFIS0 0 OEHS
FUNCTION
Increment delay H sync begin, 50 Hz H sync stop, 50 Hz H clamp begin, 50 Hz H clamp stop, 50 Hz H sync after PHI1, 50 Hz Luminance control Hue control Colour killer threshold QAM
CORI0 APER1 HUEC2 HUEC1 0 0 0 PLSE2 SESE2 0 HRMV CHRS 0 PLSE1 SESE1
Colour-killer threshold SECAM 09 PAL switch sensitivity 0A SECAM switch sensitivity 0B Chroma gain control settings Standard/mode control I/O and clock control Control #1 Control #2 Chroma gain reference Not used, is acknowledged Not used, is acknowledged H sync begin, 60 Hz H sync stop, 60 Hz H clamp begin, 60 Hz H clamp stop, 60 Hz H sync after PHI1, 60 Hz Notes 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
0 0 GPSW0 SECS GPSW2 GPSW1 YDEL0 VNOI0 CHCV0 0 0 HS6B0 HS6S0 HC6B0 HC6S0 HP6I0
AUFD FSEL SXCR 0 0 0 CHCV7 CHCV6 CHCV5 0 0 HS6B7 HS6S7 0 0 HS6B6 HS6S6 0 0 HS6B5 HS6S5
YDEL2 YDEL1 HRFS VNOI1 CHCV2 CHCV1 0 0 HS6B2 HS6S2 HC6B2 HC6S2 HP6I2 0 0 HS6B1 HS6S1 HC6B1 HC6S1 HP6I1
HC6B7 HC6B6 HC6B5 HC6S7 HC6S6 HC6S5 HP6I7 HP6I6 HP6I5
1. Default values of register contents to obtain a picture see Table 6. 2. All unused control bits must be programmed with "0" (zero) as indicated in Table 5.
August 1996
26
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
Function of the bits of Table 5 IDEL7 "00" to IDEL0
SAA7191B
Increment delay time (dependent on application), step size = 4 / LLC. The delay time is selectable from -4 / LLC (-1 decimal multiplier) to -1024 / LLC (-256 decimal multiplier) equals data FF to 00 (hex). Different processing times in the chrominance channel and the clock generation could result in phase errors in the chrominance processing by transients in clock frequency. An adjustable delay (IDEL) is necessary if the processing time in the clock generation is unknown. Horizontal sync begin for 50 Hz, step size = 2 / LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BF to C0 (hex). Two's complement numbers with "hidden" sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal sync stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BF to C0 (hex). Two's complement numbers with "hidden" sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal clamp start for 50 Hz, step size = 2 / LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7F to 80 (hex). Horizontal clamp stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7F to 80 (hex). Horizontal sync after PHI1 for 50 Hz, step size = 8 / LLC. The delay time is selectable from -936 /LLC (+117 decimal multiplier) to +944/LLC (-118 decimal multiplier) equals data 75 to 8A (hex). input mode select bit: 0 = CVBS mode (chrominance trap active) 1 = S-Video mode (chrominance trap bypassed) use of pre-filter: 0 = pre-filter off; 1 = pre-filter on; PREF may be used if chrominance trap is active.
HSYB7 "01"
to
HSYB0
HSYS7 "02"
to
HSYS0
HCLB7 "03" HCLS7 "04" HPHI7 "05" BYPS "06" PREF
to
HCLB0
to
HCLS0
to
HPHI0
-------------- ---------------------------------------------------
-------------- --------------------------------------------------- BPSS1 to BPSS0 Aperture bandpass to select different characteristics with maximums (0.2 to 0.3 x LLC / 2): BPSS1 0 0 1 1 CORI1 "06" to CORI0 BPSS0 0 1 0 1 characteristics ) ) ) ) Figures 16 to 25
-------------- ---------------------------------------------------- Coring range for high frequency components according to 8-bit luminance, Fig.15. CORI1 0 0 1 1 CORI0 0 1 0 1 coring coring off 1 LSB 2 LSB 3 LSB
August 1996
27
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
APER1 "06" to APER0
SAA7191B
Aperture bandpass filter weights high frequency components of luminance signal: APER1 0 0 1 1 APER0 0 1 0 1 factor 0 0.25 0.5 1 ) ) ) ) Figure 16 to 25
HUE7 "07" CKTQ4 "08" CKTS4 "09" PLSE7 "0A" SESE7 "0B" COLO "0C" LFIS1 "0C"
to to to to to
HUE0 CKTQ0 CKTS0 PLSE0 SESE0
Hue control from +178.6 to -180.0, equals data bytes 7F to 80 (hex); 0 equals 00. Colour-killer threshold QAM from approximately -30 dB to -18 dB, equals data bytes F8 to 07 (hex) Colour-killer threshold SECAM from approximately -30 dB to -18 dB, equals data bytes. F8 to 07 (hex) PAL switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. SECAM switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. Colour on bit: 0 = automatic colour-killer enabled; 1 = forced colour on.
-------------- ---------------------------------------------------- to LFIS0 Chrominance gain control (AGC filter): LFIS1 0 0 1 1 VTRC "0D" NFEN LFIS0 0 1 0 1 = = = = loop filter time constant slow medium fast actual gain, stored for test purposes only
VTR/TV mode bit : 0 = TV mode (slow time constant); 1 = VTR mode (fast time constant)
-------------- ---------------------------------------------------- SAA7191B-specified functions enable (RTCO, ODD and GPSW0 outputs) 0 = outputs set to high-impedance (circuit equals SAA7191); 1 = outputs active HREF generation: 0 = like SAA7191; General purpose switch 0: 1 = HREF is 8 x LLC2 clocks earlier
-------------- ---------------------------------------------------- HRMV GPSWO SECS 0 = output pin 65 LOW; 1 = output pin 65 HIGH
-------------- ---------------------------------------------------- SECAM mode bit : 0 = other standards; 1 = SECAM
August 1996
28
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
HPLL "0E" OEDC
SAA7191B
Horizontal clock PLL: 0 = PLL closed; 1 = PLL circuit open and horizontal frequency fixed. Colour-difference output enable: 0 = data outputs UV7 to UV0 can be set to high-impedance via FEIN 1 = data outputs UV7 to UV0 active. 0 = HS and HREF outputs high-impedance 1 = HS and HREF outputs active.
-------------- ----------------------------------------------------
-------------- ---------------------------------------------------- OEHS H-sync output enable (pins 31 and 42):
-------------- ---------------------------------------------------- OEVS OEDY V-sync output enable (pin 30): 0 = VS output high-impedance 1 = VS output active.
Luminance output enable: 0 = data outputs Y7 to Y0 can be set to high-impedance via FEIN 1 = data outputs Y7 to Y0 active. S-VHS bit (chrominance from CVBS or from chrominance input): 0 = controlled by BYPS-bit (subaddress 06) 1 = chrominance from chrominance input (CHR7 to CHR0) to GPSW1 General purpose switches: GPSW2 0 0 1 1 GPSW1 0 1 0 1 set port output pins 24 (GPSW2) and 25 (GPSW1) use is dependent on application
-------------- ---------------------------------------------------- CHRS
-------------- ---------------------------------------------------- GPSW2 to "0E"
August 1996
29
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
AUFD "0F" FSEL Automatic field detection: 0 = field selection by FSEL-bit; 1 = automatic field detection. 0 = 50 Hz (625 lines); 1 = 60 Hz (525 lines) 0 = reduction off; 1 = reduction on.
SAA7191B
-------------- ---------------------------------------------------- Field select (AUFD-bit = 0):
-------------- ---------------------------------------------------- SXCR SECAM cross-colour reduction:
-------------- ---------------------------------------------------- SCEN Sync and clamping pulse enable: 0 = HCL and HSY outputs HIGH (pins 26 and 29); 1 = HCL and HSY outputs active 0 = 4 : 1 : 1 format; 1 = 4 : 2 : 2 format.
-------------- ---------------------------------------------------- OFTS Select output format:
-------------- ---------------------------------------------------- YDEL2 to YDEL0 Luminance delay compensation: YDEL2 0 0 0 0 1 1 1 1 HFRS "10" YDEL1 0 0 1 1 0 0 1 1 YDEL0 0 1 0 1 0 1 0 1 figure 0 x 2 / LLC +1 x 2 / LLC +2 x 2 / LLC +3 x 2 / LLC -4 x 2 / LLC -3 x 2 / LLC -2 x 2 / LLC -1 x 2 / LLC
step size = 2 / LLC = 67.8 ns for 50 Hz 81.5 ns for 60 Hz
Select HREF position:
0 = normal, HREF is matched to YUV output port; 1 = HREF is matched to CVBS input port.
-------------- ---------------------------------------------------- VNOI1 to VNOI0 Vertical noise reduction VNOI1 0 0 1 1 CHCV7U V to CHCV0 "11" VNOI0 0 1 0 1 mode normal searching window auto-deflection vertical noise reduction bypassed
Chrominance gain control (nominal values) for QAM-modulated input signals, effects output amplitude (SECAM with fixed gain): D7 D6 D5 D4 1 0 0 0 1 : 1 : 0 : 0 1 0 1 0 1 1 0 0 D3 D2 D1 D0 1 1 1 0 1 : 0 : 1 : 0 1 0 0 0 1 1 0 0 gain maximum gain to CCIR level for PAL) to CCIR level for NTSC) to minimum gain ) ) default programmed ) values dependent ) on application )
August 1996
30
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
HS6B7 "14" to HS6B0
SAA7191B
Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BF to C0 (hex). Two's complement numbers with "hidden" sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BF to C0 (hex). Two's complement numbers with "hidden" sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal clamp begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7F to 80 (hex). Horizontal clamp stop for 60 Hz, step size = 2 / LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7F to 80 (hex). Horizontal sync after PHI1 for 60 Hz, step size = 8 / LLC. The delay time is selectable from -776/LLC (+97 decimal multiplier) to +776 /LLC (-97 decimal multiplier) equals data 61 to 9F (hex).
HS6S7 "15"
to
HS6S0
HC6B7 "16" HC6S7 "17" HP6I7 "18"
to
HC6B0
to
HC6S0
to
HP6I0
MEH228
handbook, full pagewidth
bits +64
+32 (b) (a) 0 (a) (b) -32 (c)
(c)
-64 -64 -32 0 +32 +64 bits
(a) (b) (c)
CORI1 = 0; CORI0 = 1 CORI1 = 1; CORI0 = 0 CORI1 = 1; CORI0 = 1
Fig.15 Coring function adjustment by subaddress 06 to affect the bandfilter output signal. The thresholds are related to the 13-bit word width in the luminance processing part and influence the 1LSB to 3LSB (Y0 to Y2) with respect to the 8-bit luminance output
August 1996
31
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
handbook, full pagewidth
SAA7191B
18 63h 12
MEH214
73h
VY (dB)
43h 6 53h 0
43h
53h
-6 63h -12
73h
-18
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.16 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture bandpass filter characteristic.
handbook, full pagewidth
18 62h 61h 12 42h
MEH215
VY (dB)
6 42h 41h 0 62h 40h -6 61h -12 40h 41h
-18
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.17 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture bandpass filter characteristics.
August 1996
32
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, full pagewidth
18 23h 12 33h
MEH216
VY (dB)
6 13h 0 13h -6 00h -12 00h -18 23h 03h 03h 33h
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.18 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum aperture bandpass filter characteristic.
handbook, full pagewidth
18 73h 12
MEH217
VY (dB) 6
63h 43h 53h 43h 53h
0 63h -6 73h
-12
-18
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.19 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture bandpass filter characteristic.
August 1996
33
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
MEH218
SAA7191B
handbook, full pagewidth
18 61h 12
VY (dB)
62h
42h
6 41h 50h 0 62h 43h 42h
-6 50h 61h -12
-18
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.20 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture bandpass filter characteristics.
handbook, full pagewidth
18 33h 12
MEH219
VY (dB)
23h 6 13h 03h 13h 03h 0 33h
-6 00h -12 23h 00h
-18
-24
-30
0
1
2
3
4
5 f Y (MHz)
6
Fig.21 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum and minimum aperture bandpass filter characteristics.
August 1996
34
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
SAA7191B
handbook, halfpage
18 12
MEH220
handbook, halfpage
18 12 6
MEH221
C3h C2h
VY (dB)
83h 6 0 81h -6 -12 -18 0 2 4 6 80h
82h
VY (dB)
C1h 0 -6 -12 -18 8 f Y (MHz) 0 2 4 6 f Y (MHz) 8 C0h
Fig.22 Luminance control in 50 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture bandpass filter characteristics.
Fig.23 Luminance control in 50 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture bandpass filter characteristics.
handbook, halfpage
18 12
MEH222
handbook, halfpage
18 12
MEH223
C3h C2h
VY (dB)
83h 6 0 81h -6 -12 -18 0 2 4 6
82h
VY (dB)
6 C1h 0 80h C0h -6 -12 -18 8 f Y (MHz) 0 2 4 6 f Y (MHz) 8
Fig.24 Luminance control in 60 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture bandpass filter characteristics.
Fig.25 Luminance control in 60 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture bandpass filter characteristics.
August 1996
35
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
11 PROGRAMMING EXAMPLE
SAA7191B
Coefficients to set operation for application circuits Figures 13 and 14. (All numbers of the Table 6 are hex values). Slave address byte is 8A at pin 43 = 0 V (or 8E at pin 43 = +5 V). Table 7 Recommended default values BIT NAME IDEL(7-0) HSYB(7-0) HSYS(7-0) HCLB(7-0) HCLS(7-0) HPHI(7-0) BYPS, PREF, BPSS(1-0) CORI(1-0), APER(1-0) HUEC(7-0) CKTQ(4-0) CKTS(4-0) PLSE(7-0) SESE(7-0) COLO, LFIS(1-0) VTRC, NFEN,HRMV, GPSW0 and SECS HPLL, OEDC, OEHS, OEVS OEDY, CHRS, GPSW(2-1) AUFD, FSEL, SXCR, SCEN, OFTS, YDEL(2-0) HRFS, VNOI(1-0) CHCV(7-0) - - HS6B(7-0) HS6S(7-0) HC6B(7-0) HC6S(7-0) HP6I(7-0) luminance bandwidth control: hue control (0 degree) colour-killer threshold QUAM colour-killer threshold SECAM PAL switch sensitivity SECAM switch sensitivity chroma gain control settings standard/mode control I/O and clock control miscellaneous control #1 miscellaneous control #2 chrominance gain nominal value set to zero set to zero H sync beginning for 60 Hz H sync stop for 60 Hz H clamping beginning for 60 Hz H clamping stop for 60 Hz H sync position for 60 Hz 01(1) 00 F8 F8 90 90 00 00(2)(4), 01(3)(4) 79, 7E(5) 91(6), 99(7) 00 2C(8), 59(9) 00 00 ----------- 34 0A F4 CE F4 FUNCTION increment delay H sync beginning for 50 Hz H sync stop for 50 Hz H clamping beginning for 50 Hz H clamping stop for 50 Hz H sync position for 50 Hz 50 30 00 E8 B6 F4 ----------- VALUE (HEX)
SUBADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 Notes
--------- ----------------- ----------------
--------- ----------------- ----------------
1. dependent on application (Figures 16 to 25) 2. for QUAM standards 3. for SECAM 4. HPLL is in TV mode; value for VCR mode is 80 (81 for SECAM VCR mode) 5. for Y/C mode 6. 4:1:1 format
7. 4:2:2 format 8. nominal value for UV CCIR level with NTSC source 9. nominal value for UV CCIR level with PAL source
August 1996
36
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
12 PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7191B
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
August 1996
37
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
13 SOLDERING 13.1 Introduction 13.3 Wave soldering
SAA7191B
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 13.2 Reflow soldering
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints
Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
August 1996
38
Philips Semiconductors
Product specification
Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP)
14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7191B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
August 1996
39
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657027/00/01/pp40
Date of release: August 1996
Document order number:
9397 750 02437

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